MAX11647EUA+T【PDF 6/22 页】IC ADC 10BIT I2C 94.4KSPS 8UMAX

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MAX11646/MAX11647

Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs

in Ultra-Tiny 1.9mm x 2.2mm Package

______________________________________________________________________________________

Configuration/Setup Bytes (Write Cycle)

A write cycle begins with the bus master issuing a

START condition followed by 7 address bits (Figure 7)

and a write bit (R/W = 0). If the address byte is success-

fully received, the MAX11646/MAX11647 (slave) issue

an acknowledge. The master then writes to the slave.

The slave recognizes the received byte as the setup

byte (Table 1) if the most significant bit (MSB) is 1. If the

MSB is 0, the slave recognizes that byte as the configu-

ration byte (Table 2). The master can write either 1 or 2

bytes to the slave in any order (setup byte then configu-

ration byte, configuration byte then setup byte, setup

byte or configuration byte only; see Figure 9). If the

slave receives a byte successfully, it issues an acknowl-

edge. The master ends the write cycle by issuing a

STOP condition or a repeated START condition. When

operating in HS mode, a STOP condition returns the bus

into F/S mode (see the

HS Mode section).

B. 2-BYTE WRITE CYCLE

SLAVE TO MASTER

MASTER TO SLAVE

SLAVE ADDRESS

71 1

SETUP OR

CONFIGURATION BYTE

SETUP OR

CONFIGURATION BYTE

P or Sr

MSB DETERMINES WHETHER

SETUP OR CONFIGURATION BYTE

SLAVE ADDRESS

71 1

SETUP OR

CONFIGURATION BYTE

P or Sr

MSB DETERMINES WHETHER

SETUP OR CONFIGURATION BYTE

A. 1-BYTE WRITE CYCLE

NUMBER OF BITS

Figure 9. Write Cycle

BIT 7

(MSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

(LSB)

REG

SEL2

SEL1

SEL0

CLK

BIP/UNI

RST

BIT

NAME

DESCRIPTION

REG

SEL2

SEL1

SEL0

Three bits select the reference voltage (Table 6). Default to 000 at power-up.

CLK

1 = external clock, 0 = internal clock. Defaulted to 0 at power-up.

BIP/UNI

1 = bipolar, 0 = unipolar. Defaulted to 0 at power-up (see the Unipolar/Bipolar section).

RST

1 = no action, 0 = resets the configuration register to default. Setup register remains unchanged.

Don’t-care bit. This bit can be set to 1 or 0.

Table 1. Setup Byte Format

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